diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..89cc49c
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+.pio
+.vscode/.browse.c_cpp.db*
+.vscode/c_cpp_properties.json
+.vscode/launch.json
+.vscode/ipch
diff --git a/.vscode/extensions.json b/.vscode/extensions.json
new file mode 100644
index 0000000..0f0d740
--- /dev/null
+++ b/.vscode/extensions.json
@@ -0,0 +1,7 @@
+{
+    // See http://go.microsoft.com/fwlink/?LinkId=827846
+    // for the documentation about the extensions.json format
+    "recommendations": [
+        "platformio.platformio-ide"
+    ]
+}
diff --git a/include/README b/include/README
new file mode 100644
index 0000000..194dcd4
--- /dev/null
+++ b/include/README
@@ -0,0 +1,39 @@
+
+This directory is intended for project header files.
+
+A header file is a file containing C declarations and macro definitions
+to be shared between several project source files. You request the use of a
+header file in your project source file (C, C++, etc) located in `src` folder
+by including it, with the C preprocessing directive `#include'.
+
+```src/main.c
+
+#include "header.h"
+
+int main (void)
+{
+ ...
+}
+```
+
+Including a header file produces the same results as copying the header file
+into each source file that needs it. Such copying would be time-consuming
+and error-prone. With a header file, the related declarations appear
+in only one place. If they need to be changed, they can be changed in one
+place, and programs that include the header file will automatically use the
+new version when next recompiled. The header file eliminates the labor of
+finding and changing all the copies as well as the risk that a failure to
+find one copy will result in inconsistencies within a program.
+
+In C, the usual convention is to give header files names that end with `.h'.
+It is most portable to use only letters, digits, dashes, and underscores in
+header file names, and at most one dot.
+
+Read more about using header files in official GCC documentation:
+
+* Include Syntax
+* Include Operation
+* Once-Only Headers
+* Computed Includes
+
+https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html
diff --git a/lib/README b/lib/README
new file mode 100644
index 0000000..6debab1
--- /dev/null
+++ b/lib/README
@@ -0,0 +1,46 @@
+
+This directory is intended for project specific (private) libraries.
+PlatformIO will compile them to static libraries and link into executable file.
+
+The source code of each library should be placed in a an own separate directory
+("lib/your_library_name/[here are source files]").
+
+For example, see a structure of the following two libraries `Foo` and `Bar`:
+
+|--lib
+|  |
+|  |--Bar
+|  |  |--docs
+|  |  |--examples
+|  |  |--src
+|  |     |- Bar.c
+|  |     |- Bar.h
+|  |  |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html
+|  |
+|  |--Foo
+|  |  |- Foo.c
+|  |  |- Foo.h
+|  |
+|  |- README --> THIS FILE
+|
+|- platformio.ini
+|--src
+   |- main.c
+
+and a contents of `src/main.c`:
+```
+#include <Foo.h>
+#include <Bar.h>
+
+int main (void)
+{
+  ...
+}
+
+```
+
+PlatformIO Library Dependency Finder will find automatically dependent
+libraries scanning project source files.
+
+More information about PlatformIO Library Dependency Finder
+- https://docs.platformio.org/page/librarymanager/ldf.html
diff --git a/platformio.ini b/platformio.ini
new file mode 100644
index 0000000..ffd63bf
--- /dev/null
+++ b/platformio.ini
@@ -0,0 +1,15 @@
+; PlatformIO Project Configuration File
+;
+;   Build options: build flags, source filter
+;   Upload options: custom upload port, speed and extra flags
+;   Library options: dependencies, extra library storages
+;   Advanced options: extra scripting
+;
+; Please visit documentation for the other options and examples
+; https://docs.platformio.org/page/projectconf.html
+
+[env:nanoatmega328]
+platform = atmelavr
+board = nanoatmega328
+framework = arduino
+lib_deps = wayoda/LedControl@^1.0.6
diff --git a/schema/max-7seg-clock/7seg.dcm b/schema/max-7seg-clock/7seg.dcm
new file mode 100644
index 0000000..c10d035
--- /dev/null
+++ b/schema/max-7seg-clock/7seg.dcm
@@ -0,0 +1,15 @@
+EESchema-DOCLIB  Version 2.0
+#
+$CMP 5161AS
+D One digit 7 segment red, common cathode
+K display LED 7-segment
+F https://docs.broadcom.com/docs/AV02-2553EN
+$ENDCMP
+#
+$CMP HDSP-7503
+D One digit 7 segment high efficiency red, common cathode
+K display LED 7-segment
+F https://docs.broadcom.com/docs/AV02-2553EN
+$ENDCMP
+#
+#End Doc Library
diff --git a/schema/max-7seg-clock/7seg.lib b/schema/max-7seg-clock/7seg.lib
new file mode 100644
index 0000000..86471e6
--- /dev/null
+++ b/schema/max-7seg-clock/7seg.lib
@@ -0,0 +1,46 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 5161AS
+#
+DEF 5161AS U 0 20 Y Y 1 F N
+F0 "U" -150 550 50 H V C CNN
+F1 "5161AS" 250 550 50 H V C CNN
+F2 "Display_7Segment:5161AS" 0 -550 50 H I C CNN
+F3 "" -400 550 50 H I C CNN
+ALIAS HDSP-7503
+$FPLIST
+ HDSP?A151*
+$ENDFPLIST
+DRAW
+T 0 10 95 20 0 1 0 A Normal 0 C C
+T 0 100 65 20 0 1 0 B Normal 0 C C
+T 0 90 -55 20 0 1 0 C Normal 0 C C
+T 0 -10 -85 20 0 1 0 D Normal 0 C C
+T 0 140 -115 20 0 1 0 DP Normal 0 C C
+T 0 -100 -55 20 0 1 0 E Normal 0 C C
+T 0 -90 65 20 0 1 0 F Normal 0 C C
+T 0 0 35 20 0 1 0 G Normal 0 C C
+S -200 500 200 -500 1 1 10 f
+P 2 1 1 20 -60 -15 -70 -95 N
+P 2 1 1 20 -50 -115 30 -115 N
+P 2 1 1 20 -50 105 -60 25 N
+P 2 1 1 20 -40 5 40 5 N
+P 2 1 1 20 -30 125 50 125 N
+P 2 1 1 20 60 -15 50 -95 N
+P 2 1 1 20 70 105 60 25 N
+P 2 1 1 20 100 -115 100 -115 N
+X E 1 -300 -100 100 R 50 50 1 1 I
+X G 10 -300 -300 100 R 50 50 1 1 I
+X D 2 -300 0 100 R 50 50 1 1 I
+X CC 3 300 -300 100 L 50 50 1 1 I
+X C 4 -300 100 100 R 50 50 1 1 I
+X DP 5 -300 -400 100 R 50 50 1 1 I
+X B 6 -300 200 100 R 50 50 1 1 I
+X A 7 -300 300 100 R 50 50 1 1 I
+X CC 8 300 -400 100 L 50 50 1 1 I
+X F 9 -300 -200 100 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/schema/max-7seg-clock/7seg.pretty/7SegmentLED_LTS6760_LTS6780.kicad_mod b/schema/max-7seg-clock/7seg.pretty/7SegmentLED_LTS6760_LTS6780.kicad_mod
new file mode 100644
index 0000000..ec93edf
--- /dev/null
+++ b/schema/max-7seg-clock/7seg.pretty/7SegmentLED_LTS6760_LTS6780.kicad_mod
@@ -0,0 +1,49 @@
+(module 7SegmentLED_LTS6760_LTS6780 (layer F.Cu) (tedit 5FFF72B2)
+  (descr "7-Segment Display, LTS67x0, http://optoelectronics.liteon.com/upload/download/DS30-2001-355/S6760jd.pdf")
+  (tags "7Segment LED LTS6760 LTS6780")
+  (fp_text reference REF** (at 7.62 -2.42) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value 7SegmentLED_5161AS (at 7.62 12.58) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start 1.905 -1.33) (end 13.335 -1.33) (layer F.SilkS) (width 0.12))
+  (fp_line (start 1.905 11.49) (end 13.335 11.49) (layer F.SilkS) (width 0.12))
+  (fp_line (start -2.015 -0.22) (end -2.015 11.38) (layer F.SilkS) (width 0.12))
+  (fp_line (start 17.255 11.38) (end 17.255 -1.22) (layer F.SilkS) (width 0.12))
+  (fp_line (start -2.16 -1.47) (end -2.16 11.63) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 17.4 -1.47) (end 17.4 11.63) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -2.16 -1.47) (end 17.4 -1.47) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -2.16 11.63) (end 17.4 11.63) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -0.905 -1.22) (end -1.905 -0.22) (layer F.Fab) (width 0.1))
+  (fp_line (start 17.145 11.38) (end 17.145 -1.22) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.905 -0.22) (end -1.905 11.38) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.905 11.38) (end 17.145 11.38) (layer F.Fab) (width 0.1))
+  (fp_line (start 12.62 2.08) (end 7.62 1.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start 7.62 1.08) (end 2.62 0.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start 2.62 0.08) (end 2.62 7.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start 2.62 7.08) (end 7.62 8.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start 12.62 9.08) (end 7.62 8.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start 7.62 8.08) (end 7.62 1.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start 12.62 2.08) (end 12.62 9.08) (layer F.SilkS) (width 0.12))
+  (fp_circle (center 2.62 9.08) (end 3.067214 9.08) (layer F.SilkS) (width 0.12))
+  (fp_line (start -0.905 -1.22) (end 17.145 -1.22) (layer F.Fab) (width 0.1))
+  (fp_text user %R (at 7.87 5.08) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (pad 10 thru_hole oval (at 15.24 0 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 9 thru_hole oval (at 15.24 2.54 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 8 thru_hole oval (at 15.24 5.08 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 7 thru_hole oval (at 15.24 7.62 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 6 thru_hole oval (at 15.24 10.16 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 5 thru_hole oval (at 0 10.16 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 4 thru_hole oval (at 0 7.62 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 3 thru_hole oval (at 0 5.08 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 2 thru_hole oval (at 0 2.54 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 1 thru_hole rect (at 0 0 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask))
+  (model ${KISYS3DMOD}/Display_7Segment.3dshapes/7SegmentLED_LTS6760_LTS6780.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 1 1 1))
+    (rotate (xyz 0 0 0))
+  )
+)
diff --git a/schema/max-7seg-clock/7seg.pretty/DIP-28_W15.24mm_Socket_Large_Holes.kicad_mod b/schema/max-7seg-clock/7seg.pretty/DIP-28_W15.24mm_Socket_Large_Holes.kicad_mod
new file mode 100644
index 0000000..31a8381
--- /dev/null
+++ b/schema/max-7seg-clock/7seg.pretty/DIP-28_W15.24mm_Socket_Large_Holes.kicad_mod
@@ -0,0 +1,69 @@
+(module DIP-28_W15.24mm_Socket_Large_Holes (layer F.Cu) (tedit 600DB720)
+  (descr "28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket")
+  (tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket")
+  (fp_text reference REF** (at 7.62 -2.33) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value DIP-28_W15.24mm_Socket_Large_Holes (at 7.62 35.35) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+  (fp_text user %R (at 7.62 16.51) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start 16.8 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 16.8 34.65) (end 16.8 -1.6) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -1.55 34.65) (end 16.8 34.65) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -1.55 -1.6) (end -1.55 34.65) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 16.57 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
+  (fp_line (start 16.57 34.41) (end 16.57 -1.39) (layer F.SilkS) (width 0.12))
+  (fp_line (start -1.33 34.41) (end 16.57 34.41) (layer F.SilkS) (width 0.12))
+  (fp_line (start -1.33 -1.39) (end -1.33 34.41) (layer F.SilkS) (width 0.12))
+  (fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
+  (fp_line (start 14.08 34.35) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
+  (fp_line (start 1.16 34.35) (end 14.08 34.35) (layer F.SilkS) (width 0.12))
+  (fp_line (start 1.16 -1.33) (end 1.16 34.35) (layer F.SilkS) (width 0.12))
+  (fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+  (fp_line (start 16.51 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
+  (fp_line (start 16.51 34.35) (end 16.51 -1.33) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.27 34.35) (end 16.51 34.35) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.27 -1.33) (end -1.27 34.35) (layer F.Fab) (width 0.1))
+  (fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
+  (fp_line (start 0.255 34.29) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
+  (fp_line (start 14.985 34.29) (end 0.255 34.29) (layer F.Fab) (width 0.1))
+  (fp_line (start 14.985 -1.27) (end 14.985 34.29) (layer F.Fab) (width 0.1))
+  (fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
+  (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 15 thru_hole oval (at 15.24 33.02) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 16 thru_hole oval (at 15.24 30.48) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 17 thru_hole oval (at 15.24 27.94) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 18 thru_hole oval (at 15.24 25.4) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 19 thru_hole oval (at 15.24 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 20 thru_hole oval (at 15.24 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 21 thru_hole oval (at 15.24 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 22 thru_hole oval (at 15.24 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 23 thru_hole oval (at 15.24 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 24 thru_hole oval (at 15.24 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 11 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 25 thru_hole oval (at 15.24 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 12 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 26 thru_hole oval (at 15.24 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 13 thru_hole oval (at 0 30.48) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 27 thru_hole oval (at 15.24 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 14 thru_hole oval (at 0 33.02) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (pad 28 thru_hole oval (at 15.24 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
+  (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-28_W15.24mm_Socket.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 1 1 1))
+    (rotate (xyz 0 0 0))
+  )
+)
diff --git a/schema/max-7seg-clock/fp-info-cache b/schema/max-7seg-clock/fp-info-cache
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/schema/max-7seg-clock/fp-info-cache
@@ -0,0 +1 @@
+0
diff --git a/schema/max-7seg-clock/fp-lib-table b/schema/max-7seg-clock/fp-lib-table
new file mode 100644
index 0000000..9a0d216
--- /dev/null
+++ b/schema/max-7seg-clock/fp-lib-table
@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name 7seg)(type KiCad)(uri ${KIPRJMOD}/7seg.pretty)(options "")(descr ""))
+)
diff --git a/schema/max-7seg-clock/max-7seg-clock-cache.lib b/schema/max-7seg-clock/max-7seg-clock-cache.lib
new file mode 100644
index 0000000..f4f8d11
--- /dev/null
+++ b/schema/max-7seg-clock/max-7seg-clock-cache.lib
@@ -0,0 +1,86 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 7seg_5161AS
+#
+DEF 7seg_5161AS U 0 20 Y Y 1 F N
+F0 "U" -150 550 50 H V C CNN
+F1 "7seg_5161AS" 250 550 50 H V C CNN
+F2 "Display_7Segment:5161AS" 0 -550 50 H I C CNN
+F3 "" -400 550 50 H I C CNN
+ALIAS HDSP-7503
+$FPLIST
+ HDSP?A151*
+$ENDFPLIST
+DRAW
+T 0 10 95 20 0 1 0 A Normal 0 C C
+T 0 100 65 20 0 1 0 B Normal 0 C C
+T 0 90 -55 20 0 1 0 C Normal 0 C C
+T 0 -10 -85 20 0 1 0 D Normal 0 C C
+T 0 140 -115 20 0 1 0 DP Normal 0 C C
+T 0 -100 -55 20 0 1 0 E Normal 0 C C
+T 0 -90 65 20 0 1 0 F Normal 0 C C
+T 0 0 35 20 0 1 0 G Normal 0 C C
+S -200 500 200 -500 1 1 10 f
+P 2 1 1 20 -60 -15 -70 -95 N
+P 2 1 1 20 -50 -115 30 -115 N
+P 2 1 1 20 -50 105 -60 25 N
+P 2 1 1 20 -40 5 40 5 N
+P 2 1 1 20 -30 125 50 125 N
+P 2 1 1 20 60 -15 50 -95 N
+P 2 1 1 20 70 105 60 25 N
+P 2 1 1 20 100 -115 100 -115 N
+X E 1 -300 -100 100 R 50 50 1 1 I
+X G 10 -300 -300 100 R 50 50 1 1 I
+X D 2 -300 0 100 R 50 50 1 1 I
+X CC 3 300 -300 100 L 50 50 1 1 I
+X C 4 -300 100 100 R 50 50 1 1 I
+X DP 5 -300 -400 100 R 50 50 1 1 I
+X B 6 -300 200 100 R 50 50 1 1 I
+X A 7 -300 300 100 R 50 50 1 1 I
+X CC 8 300 -400 100 L 50 50 1 1 I
+X F 9 -300 -200 100 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Driver_LED_MAX7219
+#
+DEF Driver_LED_MAX7219 U 0 20 Y Y 1 F N
+F0 "U" -250 950 50 H V L BNN
+F1 "Driver_LED_MAX7219" 50 1000 50 H V L TNN
+F2 "" -50 50 50 H I C CNN
+F3 "" 50 -150 50 H I C CNN
+$FPLIST
+ SOIC*7.5x15.4mm*P1.27mm*
+ DIP*7.62mm*
+$ENDFPLIST
+DRAW
+S -300 900 300 -900 0 1 10 f
+X DIN 1 -400 -800 100 R 50 50 1 1 I
+X DIG_5 10 400 -500 100 L 50 50 1 1 O
+X DIG_1 11 400 -100 100 L 50 50 1 1 O
+X LOAD 12 -400 -600 100 R 50 50 1 1 I
+X CLK 13 -400 -700 100 R 50 50 1 1 I
+X SEG_A 14 400 800 100 L 50 50 1 1 O
+X SEG_F 15 400 300 100 L 50 50 1 1 O
+X SEG_B 16 400 700 100 L 50 50 1 1 O
+X SEG_G 17 400 200 100 L 50 50 1 1 O
+X ISET 18 -400 800 100 R 50 50 1 1 I
+X V+ 19 0 1000 100 D 50 50 1 1 W
+X DIG_0 2 400 0 100 L 50 50 1 1 O
+X SEG_C 20 400 600 100 L 50 50 1 1 O
+X SEG_E 21 400 400 100 L 50 50 1 1 O
+X SEG_DP 22 400 100 100 L 50 50 1 1 O
+X SEG_D 23 400 500 100 L 50 50 1 1 O
+X DOUT 24 400 -800 100 L 50 50 1 1 O
+X DIG_4 3 400 -400 100 L 50 50 1 1 O
+X GND 4 0 -1000 100 U 50 50 1 1 W
+X DIG_6 5 400 -600 100 L 50 50 1 1 O
+X DIG_2 6 400 -200 100 L 50 50 1 1 O
+X DIG_3 7 400 -300 100 L 50 50 1 1 O
+X DIG_7 8 400 -700 100 L 50 50 1 1 O
+X GND 9 0 -1000 100 U 50 50 1 1 P N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/schema/max-7seg-clock/max-7seg-clock.kicad_pcb b/schema/max-7seg-clock/max-7seg-clock.kicad_pcb
new file mode 100644
index 0000000..008b617
--- /dev/null
+++ b/schema/max-7seg-clock/max-7seg-clock.kicad_pcb
@@ -0,0 +1,185 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.1.9+dfsg1-1)
+
+  (general
+    (thickness 1.6)
+    (drawings 0)
+    (tracks 0)
+    (zones 0)
+    (modules 1)
+    (nets 11)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(U1-Pad1)")
+  (net 2 "Net-(U1-Pad2)")
+  (net 3 "Net-(U1-Pad3)")
+  (net 4 "Net-(U1-Pad4)")
+  (net 5 "Net-(U1-Pad5)")
+  (net 6 "Net-(U1-Pad6)")
+  (net 7 "Net-(U1-Pad7)")
+  (net 8 "Net-(U1-Pad8)")
+  (net 9 "Net-(U1-Pad9)")
+  (net 10 "Net-(U1-Pad10)")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net "Net-(U1-Pad1)")
+    (add_net "Net-(U1-Pad10)")
+    (add_net "Net-(U1-Pad2)")
+    (add_net "Net-(U1-Pad3)")
+    (add_net "Net-(U1-Pad4)")
+    (add_net "Net-(U1-Pad5)")
+    (add_net "Net-(U1-Pad6)")
+    (add_net "Net-(U1-Pad7)")
+    (add_net "Net-(U1-Pad8)")
+    (add_net "Net-(U1-Pad9)")
+  )
+
+  (module 7seg:7SegmentLED_LTS6760_LTS6780 (layer F.Cu) (tedit 5FFF72B2) (tstamp 60B99E85)
+    (at 130.175 66.675)
+    (descr "7-Segment Display, LTS67x0, http://optoelectronics.liteon.com/upload/download/DS30-2001-355/S6760jd.pdf")
+    (tags "7Segment LED LTS6760 LTS6780")
+    (path /60B94B6C)
+    (fp_text reference U1 (at 7.62 -2.42) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 5161AS (at 7.62 12.58) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 7.87 5.08) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.905 -1.33) (end 13.335 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.905 11.49) (end 13.335 11.49) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.015 -0.22) (end -2.015 11.38) (layer F.SilkS) (width 0.12))
+    (fp_line (start 17.255 11.38) (end 17.255 -1.22) (layer F.SilkS) (width 0.12))
+    (fp_line (start -2.16 -1.47) (end -2.16 11.63) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 17.4 -1.47) (end 17.4 11.63) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.16 -1.47) (end 17.4 -1.47) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.16 11.63) (end 17.4 11.63) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.905 -1.22) (end -1.905 -0.22) (layer F.Fab) (width 0.1))
+    (fp_line (start 17.145 11.38) (end 17.145 -1.22) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.905 -0.22) (end -1.905 11.38) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.905 11.38) (end 17.145 11.38) (layer F.Fab) (width 0.1))
+    (fp_line (start 12.62 2.08) (end 7.62 1.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start 7.62 1.08) (end 2.62 0.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.62 0.08) (end 2.62 7.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.62 7.08) (end 7.62 8.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start 12.62 9.08) (end 7.62 8.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start 7.62 8.08) (end 7.62 1.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start 12.62 2.08) (end 12.62 9.08) (layer F.SilkS) (width 0.12))
+    (fp_circle (center 2.62 9.08) (end 3.067214 9.08) (layer F.SilkS) (width 0.12))
+    (fp_line (start -0.905 -1.22) (end 17.145 -1.22) (layer F.Fab) (width 0.1))
+    (pad 1 thru_hole rect (at 0 0 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 1 "Net-(U1-Pad1)"))
+    (pad 2 thru_hole oval (at 0 2.54 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 "Net-(U1-Pad2)"))
+    (pad 3 thru_hole oval (at 0 5.08 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 "Net-(U1-Pad3)"))
+    (pad 4 thru_hole oval (at 0 7.62 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 "Net-(U1-Pad4)"))
+    (pad 5 thru_hole oval (at 0 10.16 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 "Net-(U1-Pad5)"))
+    (pad 6 thru_hole oval (at 15.24 10.16 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 "Net-(U1-Pad6)"))
+    (pad 7 thru_hole oval (at 15.24 7.62 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 "Net-(U1-Pad7)"))
+    (pad 8 thru_hole oval (at 15.24 5.08 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 "Net-(U1-Pad8)"))
+    (pad 9 thru_hole oval (at 15.24 2.54 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 "Net-(U1-Pad9)"))
+    (pad 10 thru_hole oval (at 15.24 0 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 "Net-(U1-Pad10)"))
+    (model ${KISYS3DMOD}/Display_7Segment.3dshapes/7SegmentLED_LTS6760_LTS6780.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+)
diff --git a/schema/max-7seg-clock/max-7seg-clock.kicad_pcb-bak b/schema/max-7seg-clock/max-7seg-clock.kicad_pcb-bak
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/schema/max-7seg-clock/max-7seg-clock.kicad_pcb-bak
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/schema/max-7seg-clock/max-7seg-clock.pro b/schema/max-7seg-clock/max-7seg-clock.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/schema/max-7seg-clock/max-7seg-clock.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/schema/max-7seg-clock/max-7seg-clock.sch b/schema/max-7seg-clock/max-7seg-clock.sch
new file mode 100644
index 0000000..d5883a8
--- /dev/null
+++ b/schema/max-7seg-clock/max-7seg-clock.sch
@@ -0,0 +1,115 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 7seg:5161AS U1
+U 1 1 60B94B6C
+P 5000 3250
+F 0 "U1" H 5000 3917 50  0000 C CNN
+F 1 "5161AS" H 5000 3826 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 5000 2700 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 4600 3800 50  0001 C CNN
+	1    5000 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B961CF
+P 6300 3250
+F 0 "U?" H 6300 3917 50  0000 C CNN
+F 1 "5161AS" H 6300 3826 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 6300 2700 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 5900 3800 50  0001 C CNN
+	1    6300 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B969B3
+P 5000 4500
+F 0 "U?" H 5000 5167 50  0000 C CNN
+F 1 "5161AS" H 5000 5076 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 5000 3950 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 4600 5050 50  0001 C CNN
+	1    5000 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B96E1F
+P 6350 4550
+F 0 "U?" H 6350 5217 50  0000 C CNN
+F 1 "5161AS" H 6350 5126 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 6350 4000 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 5950 5100 50  0001 C CNN
+	1    6350 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B974EA
+P 7600 3250
+F 0 "U?" H 7600 3917 50  0000 C CNN
+F 1 "5161AS" H 7600 3826 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 7600 2700 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 7200 3800 50  0001 C CNN
+	1    7600 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B97C25
+P 7650 4550
+F 0 "U?" H 7650 5217 50  0000 C CNN
+F 1 "5161AS" H 7650 5126 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 7650 4000 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 7250 5100 50  0001 C CNN
+	1    7650 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B982F9
+P 9000 3300
+F 0 "U?" H 9000 3967 50  0000 C CNN
+F 1 "5161AS" H 9000 3876 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 9000 2750 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 8600 3850 50  0001 C CNN
+	1    9000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7seg:5161AS U?
+U 1 1 60B98C63
+P 9000 4600
+F 0 "U?" H 9000 5267 50  0000 C CNN
+F 1 "5161AS" H 9000 5176 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 9000 4050 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 8600 5150 50  0001 C CNN
+	1    9000 4600
+	1    0    0    -1  
+$EndComp
+$Comp
+L Driver_LED:MAX7219 U?
+U 1 1 60B99AA4
+P 2200 2150
+F 0 "U?" H 2200 3331 50  0000 C CNN
+F 1 "MAX7219" H 2200 3240 50  0000 C CNN
+F 2 "" H 2150 2200 50  0001 C CNN
+F 3 "https://datasheets.maximintegrated.com/en/ds/MAX7219-MAX7221.pdf" H 2250 2000 50  0001 C CNN
+	1    2200 2150
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/schema/max-7seg-clock/max-7seg-clock.sch-bak b/schema/max-7seg-clock/max-7seg-clock.sch-bak
new file mode 100644
index 0000000..ec278f4
--- /dev/null
+++ b/schema/max-7seg-clock/max-7seg-clock.sch-bak
@@ -0,0 +1,27 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 7seg:5161AS U1
+U 1 1 60B94B6C
+P 5000 3250
+F 0 "U1" H 5000 3917 50  0000 C CNN
+F 1 "5161AS" H 5000 3826 50  0000 C CNN
+F 2 "7seg:7SegmentLED_LTS6760_LTS6780" H 5000 2700 50  0001 C CNN
+F 3 "https://docs.broadcom.com/docs/AV02-2553EN" H 4600 3800 50  0001 C CNN
+	1    5000 3250
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/schema/max-7seg-clock/sym-lib-table b/schema/max-7seg-clock/sym-lib-table
new file mode 100644
index 0000000..33540d4
--- /dev/null
+++ b/schema/max-7seg-clock/sym-lib-table
@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name 7seg)(type Legacy)(uri ${KIPRJMOD}/7seg.lib)(options "")(descr ""))
+)
diff --git a/test/README b/test/README
new file mode 100644
index 0000000..b94d089
--- /dev/null
+++ b/test/README
@@ -0,0 +1,11 @@
+
+This directory is intended for PlatformIO Unit Testing and project tests.
+
+Unit Testing is a software testing method by which individual units of
+source code, sets of one or more MCU program modules together with associated
+control data, usage procedures, and operating procedures, are tested to
+determine whether they are fit for use. Unit testing finds problems early
+in the development cycle.
+
+More information about PlatformIO Unit Testing:
+- https://docs.platformio.org/page/plus/unit-testing.html