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Schema, RTC

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This commit is contained in:
Stefan Ostermann
2021-07-11 23:49:37 +02:00
parent 5b8935059d
commit a51ee17f7c
13 changed files with 88195 additions and 194 deletions
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schema/d1-clock.zz.fzz Normal file
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schema/max-7seg-clock/fp-info-cache
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schema/max-7seg-clock/max-7seg-clock-cache.lib
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@@ -83,4 +83,100 @@ X GND 9 0 -1000 100 U 50 50 1 1 P N
ENDDRAW
ENDDEF
#
# MCU_Module_WeMos_D1_mini
#
DEF MCU_Module_WeMos_D1_mini U 0 20 Y Y 1 F N
F0 "U" 150 750 50 H V L CNN
F1 "MCU_Module_WeMos_D1_mini" 50 -750 50 H V L CNN
F2 "Module:WEMOS_D1_mini_light" 0 -1150 50 H I C CNN
F3 "" -1850 -1150 50 H I C CNN
$FPLIST
WEMOS*D1*mini*
$ENDFPLIST
DRAW
S -300 700 300 -700 1 1 10 f
X ~RST 1 -400 400 100 R 50 50 1 1 I
X GND 10 0 -800 100 U 50 50 1 1 W
X D4 11 400 0 100 L 50 50 1 1 B
X D3 12 400 100 100 L 50 50 1 1 B
X SDA/D2 13 400 200 100 L 50 50 1 1 B
X SCL/D1 14 400 300 100 L 50 50 1 1 B
X RX 15 -400 100 100 R 50 50 1 1 I
X TX 16 -400 0 100 R 50 50 1 1 O
X A0 2 400 500 100 L 50 50 1 1 I
X D0 3 400 400 100 L 50 50 1 1 B
X SCK/D5 4 400 -100 100 L 50 50 1 1 B
X MISO/D6 5 400 -200 100 L 50 50 1 1 B
X MOSI/D7 6 400 -300 100 L 50 50 1 1 B
X CS/D8 7 400 -400 100 L 50 50 1 1 B
X 3V3 8 100 800 100 D 50 50 1 1 w
X 5V 9 -100 800 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Timer_RTC_DS1307+
#
DEF Timer_RTC_DS1307+ U 0 20 Y Y 1 F N
F0 "U" -350 350 50 H V C CNN
F1 "Timer_RTC_DS1307+" 50 350 50 H V L CNN
F2 "Package_DIP:DIP-8_W7.62mm" 0 -500 50 H I C CNN
F3 "" 0 -200 50 H I C CNN
ALIAS DS1307N+
$FPLIST
DIP*W7.62mm*
$ENDFPLIST
DRAW
S -400 300 400 -300 0 1 10 f
X X1 1 -500 -100 100 R 50 50 1 1 I
X X2 2 -500 -200 100 R 50 50 1 1 I
X VBAT 3 0 400 100 D 50 50 1 1 W
X GND 4 0 -400 100 U 50 50 1 1 W
X SDA 5 -500 100 100 R 50 50 1 1 B
X SCL 6 -500 200 100 R 50 50 1 1 I
X SQW/OUT 7 500 0 100 L 50 50 1 1 C
X VCC 8 -100 400 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_PWR_FLAG
#
DEF power_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "power_PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
X pwr 1 0 0 0 U 50 50 0 0 w
ENDDRAW
ENDDEF
#
#End Library

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schema/max-7seg-clock/max-7seg-clock.cir Normal file
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@@ -0,0 +1,35 @@
.title KiCad schematic
U1 /A1 /A1 /D0 /A1 NC_01 /DP1 /DP1 NC_02 /DP1 /A1 5161AS
U3 /E1 /E1 /D0 /E1 NC_03 /D1 /D1 NC_04 /D1 /D1 5161AS
U2 /C1 /C1 /D0 /C1 NC_05 /B1 /B1 NC_06 /B1 /C1 5161AS
U4 /G1 /G1 /D0 /G1 NC_07 /F1 /F1 NC_08 /F1 /F1 5161AS
U0 NC_09 /D0 /D4 Net-_U0-Pad4_ /D6 /D2 /D3 /D7 Net-_U0-Pad4_ /D5 /D1 NC_10 NC_11 /A1 /F1 /B1 /G1 NC_12 NC_13 /C1 /E1 /DP1 /D1 NC_14 MAX7219
U5 /A1 /A1 /D1 /A1 NC_15 /DP1 /DP1 NC_16 /DP1 /A1 5161AS
U7 /E1 /E1 /D1 /E1 NC_17 /D1 /D1 NC_18 /D1 /D1 5161AS
U6 /C1 /C1 /D1 /C1 NC_19 /B1 /B1 NC_20 /B1 /C1 5161AS
U8 /G1 /G1 /D1 /G1 NC_21 /F1 /F1 NC_22 /F1 /F1 5161AS
U9 /A1 /A1 /D2 /A1 NC_23 /DP1 /DP1 NC_24 /DP1 /A1 5161AS
U11 /E1 /E1 /D2 /E1 NC_25 /D1 /D1 NC_26 /D1 /D1 5161AS
U10 /C1 /C1 /D2 /C1 NC_27 /B1 /B1 NC_28 /B1 /C1 5161AS
U12 /G1 /G1 /D2 /G1 NC_29 /F1 /F1 NC_30 /F1 /F1 5161AS
U13 /A1 /A1 /D3 /A1 NC_31 /DP1 /DP1 NC_32 /DP1 /A1 5161AS
U15 /E1 /E1 /D3 /E1 NC_33 /D1 /D1 NC_34 /D1 /D1 5161AS
U14 /C1 /C1 /D3 /C1 NC_35 /B1 /B1 NC_36 /B1 /C1 5161AS
U16 /G1 /G1 /D3 /G1 NC_37 /F1 /F1 NC_38 /F1 /F1 5161AS
U17 /A1 /A1 /D4 /A1 NC_39 /DP1 /DP1 NC_40 /DP1 /A1 5161AS
U19 /E1 /E1 /D4 /E1 NC_41 /D1 /D1 NC_42 /D1 /D1 5161AS
U18 /C1 /C1 /D4 /C1 NC_43 /B1 /B1 NC_44 /B1 /C1 5161AS
U20 /G1 /G1 /D4 /G1 NC_45 /F1 /F1 NC_46 /F1 /F1 5161AS
U21 /A1 /A1 /D5 /A1 NC_47 /DP1 /DP1 NC_48 /DP1 /A1 5161AS
U23 /E1 /E1 /D5 /E1 NC_49 /D1 /D1 NC_50 /D1 /D1 5161AS
U22 /C1 /C1 /D5 /C1 NC_51 /B1 /B1 NC_52 /B1 /C1 5161AS
U24 /G1 /G1 /D5 /G1 NC_53 /F1 /F1 NC_54 /F1 /F1 5161AS
U25 /A1 /A1 /D6 /A1 NC_55 /DP1 /DP1 NC_56 /DP1 /A1 5161AS
U27 /E1 /E1 /D6 /E1 NC_57 /D1 /D1 NC_58 /D1 /D1 5161AS
U26 /C1 /C1 /D6 /C1 NC_59 /B1 /B1 NC_60 /B1 /C1 5161AS
U28 /G1 /G1 /D6 /G1 NC_61 /F1 /F1 NC_62 /F1 /F1 5161AS
U29 /A1 /A1 /D7 /A1 NC_63 /DP1 /DP1 NC_64 /DP1 /A1 5161AS
U31 /E1 /E1 /D7 /E1 NC_65 /D1 /D1 NC_66 /D1 /D1 5161AS
U30 /C1 /C1 /D7 /C1 NC_67 /B1 /B1 NC_68 /B1 /C1 5161AS
U32 /G1 /G1 /D7 /G1 NC_69 /F1 /F1 NC_70 /F1 /F1 5161AS
.end

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schema/max-7seg-clock/max-7seg-clock.kicad_pcb
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schema/max-7seg-clock/max-7seg-clock.kicad_pcb-bak
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@@ -1 +1,185 @@
(kicad_pcb (version 4) (host kicad "dummy file") )
(kicad_pcb (version 20171130) (host pcbnew 5.1.9+dfsg1-1)
(general
(thickness 1.6)
(drawings 0)
(tracks 0)
(zones 0)
(modules 1)
(nets 11)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(U1-Pad1)")
(net 2 "Net-(U1-Pad2)")
(net 3 "Net-(U1-Pad3)")
(net 4 "Net-(U1-Pad4)")
(net 5 "Net-(U1-Pad5)")
(net 6 "Net-(U1-Pad6)")
(net 7 "Net-(U1-Pad7)")
(net 8 "Net-(U1-Pad8)")
(net 9 "Net-(U1-Pad9)")
(net 10 "Net-(U1-Pad10)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(U1-Pad1)")
(add_net "Net-(U1-Pad10)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad3)")
(add_net "Net-(U1-Pad4)")
(add_net "Net-(U1-Pad5)")
(add_net "Net-(U1-Pad6)")
(add_net "Net-(U1-Pad7)")
(add_net "Net-(U1-Pad8)")
(add_net "Net-(U1-Pad9)")
)
(module 7seg:7SegmentLED_LTS6760_LTS6780 (layer F.Cu) (tedit 5FFF72B2) (tstamp 60B99E85)
(at 130.175 66.675)
(descr "7-Segment Display, LTS67x0, http://optoelectronics.liteon.com/upload/download/DS30-2001-355/S6760jd.pdf")
(tags "7Segment LED LTS6760 LTS6780")
(path /60B94B6C)
(fp_text reference U1 (at 7.62 -2.42) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 5161AS (at 7.62 12.58) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 7.87 5.08) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.905 -1.33) (end 13.335 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.905 11.49) (end 13.335 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -2.015 -0.22) (end -2.015 11.38) (layer F.SilkS) (width 0.12))
(fp_line (start 17.255 11.38) (end 17.255 -1.22) (layer F.SilkS) (width 0.12))
(fp_line (start -2.16 -1.47) (end -2.16 11.63) (layer F.CrtYd) (width 0.05))
(fp_line (start 17.4 -1.47) (end 17.4 11.63) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.16 -1.47) (end 17.4 -1.47) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.16 11.63) (end 17.4 11.63) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.905 -1.22) (end -1.905 -0.22) (layer F.Fab) (width 0.1))
(fp_line (start 17.145 11.38) (end 17.145 -1.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.905 -0.22) (end -1.905 11.38) (layer F.Fab) (width 0.1))
(fp_line (start -1.905 11.38) (end 17.145 11.38) (layer F.Fab) (width 0.1))
(fp_line (start 12.62 2.08) (end 7.62 1.08) (layer F.SilkS) (width 0.12))
(fp_line (start 7.62 1.08) (end 2.62 0.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.62 0.08) (end 2.62 7.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.62 7.08) (end 7.62 8.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.62 9.08) (end 7.62 8.08) (layer F.SilkS) (width 0.12))
(fp_line (start 7.62 8.08) (end 7.62 1.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.62 2.08) (end 12.62 9.08) (layer F.SilkS) (width 0.12))
(fp_circle (center 2.62 9.08) (end 3.067214 9.08) (layer F.SilkS) (width 0.12))
(fp_line (start -0.905 -1.22) (end 17.145 -1.22) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U1-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U1-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U1-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(U1-Pad4)"))
(pad 5 thru_hole oval (at 0 10.16 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U1-Pad5)"))
(pad 6 thru_hole oval (at 15.24 10.16 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(U1-Pad6)"))
(pad 7 thru_hole oval (at 15.24 7.62 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U1-Pad7)"))
(pad 8 thru_hole oval (at 15.24 5.08 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(U1-Pad8)"))
(pad 9 thru_hole oval (at 15.24 2.54 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U1-Pad9)"))
(pad 10 thru_hole oval (at 15.24 0 270) (size 1.524 2.524) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(U1-Pad10)"))
(model ${KISYS3DMOD}/Display_7Segment.3dshapes/7SegmentLED_LTS6760_LTS6780.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
)

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schema/max-7seg-clock/max-7seg-clock.pro
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@@ -1,4 +1,4 @@
update=22/05/2015 07:44:53
update=Sa 12 Jun 2021 19:57:05 CEST
version=1
last_client=kicad
[general]
@@ -31,3 +31,13 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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schema/max-7seg-clock/max-7seg-clock.sch
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schema/max-7seg-clock/max-7seg-clock.sch-bak
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