353 lines
11 KiB
C++
353 lines
11 KiB
C++
/*
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AC101 - An AC101 Codec driver library for Arduino
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Copyright (C) 2019, Ivo Pullens, Emmission
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Inspired by:
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https://github.com/donny681/esp-adf/tree/master/components/audio_hal/driver/AC101
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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Febr 2021 modified by schreibfaul1 - set correct pll values
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March 2021 modified by schreibfaul1 - can handle two i2c instances
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May 2021 modified by schreibfaul1 - constructor changed
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Oct 2021 modified by schreibfaul1 - I2C wrong ACK in ReadReg
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Jan 2022 modified by schreibfaul1 - left right channel swapped
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Jan 2022 modified by schreibfaul1 - suppress compiler warning: left shift of negative value
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examples:
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//one I2C bus: (default behaviour)
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AC101 ac;
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ac.begin(sda, scl);
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//two I2C busses:
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TwoWire i2cBusOne = TwoWire(0);
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TwoWire i2cBusTwo = TwoWire(1);
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AC101 ac(&i2cBusOne);
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i2cBusOne.begin(sda, scl, 400000);
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*/
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#include "AC101.h"
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#define BCLK // clock over BCLK comment out: clock over MCLK
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#define AC101_ADDR 0x1A // Device address
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#define CHIP_AUDIO_RS 0x00
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#define PLL_CTRL1 0x01
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#define PLL_CTRL2 0x02
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#define SYSCLK_CTRL 0x03
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#define MOD_CLK_ENA 0x04
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#define MOD_RST_CTRL 0x05
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#define I2S_SR_CTRL 0x06
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#define I2S1LCK_CTRL 0x10
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#define I2S1_SDOUT_CTRL 0x11
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#define I2S1_SDIN_CTRL 0x12
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#define I2S1_MXR_SRC 0x13
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#define I2S1_VOL_CTRL1 0x14
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#define I2S1_VOL_CTRL2 0x15
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#define I2S1_VOL_CTRL3 0x16
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#define I2S1_VOL_CTRL4 0x17
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#define I2S1_MXR_GAIN 0x18
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#define ADC_DIG_CTRL 0x40
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#define ADC_VOL_CTRL 0x41
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#define HMIC_CTRL1 0x44
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#define HMIC_CTRL2 0x45
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#define HMIC_STATUS 0x46
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#define DAC_DIG_CTRL 0x48
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#define DAC_VOL_CTRL 0x49
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#define DAC_MXR_SRC 0x4C
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#define DAC_MXR_GAIN 0x4D
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#define ADC_APC_CTRL 0x50
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#define ADC_SRC 0x51
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#define ADC_SRCBST_CTRL 0x52
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#define OMIXER_DACA_CTRL 0x53
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#define OMIXER_SR 0x54
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#define OMIXER_BST1_CTRL 0x55
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#define HPOUT_CTRL 0x56
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#define SPKOUT_CTRL 0x58
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#define AC_DAC_DAPCTRL 0xA0
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#define AC_DAC_DAPHHPFC 0xA1
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#define AC_DAC_DAPLHPFC 0xA2
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#define AC_DAC_DAPLHAVC 0xA3
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#define AC_DAC_DAPLLAVC 0xA4
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#define AC_DAC_DAPRHAVC 0xA5
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#define AC_DAC_DAPRLAVC 0xA6
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#define AC_DAC_DAPHGDEC 0xA7
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#define AC_DAC_DAPLGDEC 0xA8
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#define AC_DAC_DAPHGATC 0xA9
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#define AC_DAC_DAPLGATC 0xAA
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#define AC_DAC_DAPHETHD 0xAB
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#define AC_DAC_DAPLETHD 0xAC
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#define AC_DAC_DAPHGKPA 0xAD
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#define AC_DAC_DAPLGKPA 0xAE
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#define AC_DAC_DAPHGOPA 0xAF
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#define AC_DAC_DAPLGOPA 0xB0
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#define AC_DAC_DAPOPT 0xB1
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#define DAC_DAP_ENA 0xB5
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#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
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const uint8_t regs[] = {
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CHIP_AUDIO_RS ,
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PLL_CTRL1 ,
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PLL_CTRL2 ,
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SYSCLK_CTRL ,
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MOD_CLK_ENA ,
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MOD_RST_CTRL ,
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I2S_SR_CTRL ,
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I2S1LCK_CTRL ,
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I2S1_SDOUT_CTRL ,
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I2S1_SDIN_CTRL ,
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I2S1_MXR_SRC ,
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I2S1_VOL_CTRL1 ,
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I2S1_VOL_CTRL2 ,
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I2S1_VOL_CTRL3 ,
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I2S1_VOL_CTRL4 ,
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I2S1_MXR_GAIN ,
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ADC_DIG_CTRL ,
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ADC_VOL_CTRL ,
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HMIC_CTRL1 ,
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HMIC_CTRL2 ,
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HMIC_STATUS ,
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DAC_DIG_CTRL ,
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DAC_VOL_CTRL ,
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DAC_MXR_SRC ,
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DAC_MXR_GAIN ,
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ADC_APC_CTRL ,
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ADC_SRC ,
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ADC_SRCBST_CTRL ,
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OMIXER_DACA_CTRL ,
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OMIXER_SR ,
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OMIXER_BST1_CTRL ,
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HPOUT_CTRL ,
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SPKOUT_CTRL ,
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AC_DAC_DAPCTRL ,
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AC_DAC_DAPHHPFC ,
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AC_DAC_DAPLHPFC ,
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AC_DAC_DAPLHAVC ,
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AC_DAC_DAPLLAVC ,
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AC_DAC_DAPRHAVC ,
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AC_DAC_DAPRLAVC ,
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AC_DAC_DAPHGDEC ,
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AC_DAC_DAPLGDEC ,
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AC_DAC_DAPHGATC ,
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AC_DAC_DAPLGATC ,
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AC_DAC_DAPHETHD ,
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AC_DAC_DAPLETHD ,
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AC_DAC_DAPHGKPA ,
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AC_DAC_DAPLGKPA ,
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AC_DAC_DAPHGOPA ,
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AC_DAC_DAPLGOPA ,
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AC_DAC_DAPOPT ,
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DAC_DAP_ENA
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};
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::WriteReg(uint8_t reg, uint16_t val)
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{
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_TwoWireInstance->beginTransmission(AC101_ADDR);
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_TwoWireInstance->write(reg);
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_TwoWireInstance->write(uint8_t((val >> 8) & 0xff));
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_TwoWireInstance->write(uint8_t(val & 0xff));
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return 0 == _TwoWireInstance->endTransmission(true);
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}
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uint16_t AC101::ReadReg(uint8_t reg)
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{
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_TwoWireInstance->beginTransmission(AC101_ADDR);
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_TwoWireInstance->write(reg);
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_TwoWireInstance->endTransmission(false);
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uint16_t val = 0u;
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if (2 == _TwoWireInstance->requestFrom(uint16_t(AC101_ADDR), uint8_t(2)))
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{
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val = uint16_t(_TwoWireInstance->read() << 8) + uint16_t(_TwoWireInstance->read());
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}
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_TwoWireInstance->endTransmission(true);
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return val;
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}
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//----------------------------------------------------------------------------------------------------------------------
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AC101::AC101( TwoWire *TwoWireInstance ){
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_TwoWireInstance = TwoWireInstance;
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::begin(int32_t sda, int32_t scl, uint32_t frequency) {
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bool ok;
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if((sda >= 0) && (scl >= 0)){
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ok = _TwoWireInstance->begin(sda, scl, frequency);
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}
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else {
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ok = true;
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}
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// Reset all registers, readback default as sanity check
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ok &= WriteReg(CHIP_AUDIO_RS, 0x123);
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delay(100);
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ok &= 0x0101 == ReadReg(CHIP_AUDIO_RS);
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ok &= WriteReg(SPKOUT_CTRL, 0xe880);
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// Enable the PLL from 256*44.1KHz MCLK source
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ok &= WriteReg(PLL_CTRL1, 0x0141);
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uint16_t N = 48 << 4; /* 512 / (M * (2*K+1)) / (CHANNELS * WORD_SIZE) -> 512 / 3 * (2 * 16) */
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uint16_t PLL_EN = 1 << 15;
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uint16_t N_f = 0<<0; /* 0.2 N */
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ok &= WriteReg(PLL_CTRL2, N | PLL_EN | N_f);
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// Clocking system
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uint16_t PLLCLK_ENA = 1<<15; /* 0: Disable, 1: Enable */
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#ifdef BCLK
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uint16_t PLL_CLK = 0x2 << 12; /* bclk1 */
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uint16_t I2S1CLK_SRC = 0x3<<8; /* PLL */
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#else
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uint16_t PLL_CLK = 0x0 << 12; /* MCLK1 */
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uint16_t I2S1CLK_SRC = 0x0<<8; /* MLCK1 */
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#endif
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uint16_t I2S1CLK_ENA = 1<<11; /* 0: Disable, 1: Enable */
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uint16_t SYSCLK_ENA = 1<<3;
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ok &= WriteReg(SYSCLK_CTRL, PLLCLK_ENA|PLL_CLK| I2S1CLK_ENA|I2S1CLK_SRC|SYSCLK_ENA/*0x8b08*/);
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ok &= WriteReg(MOD_CLK_ENA, 0x800c);
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ok &= WriteReg(MOD_RST_CTRL, 0x800c);
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// Set default at I2S, 44.1KHz, 16bit
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ok &= SetI2sSampleRate(SAMPLE_RATE_44100);
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ok &= SetI2sClock(BCLK_DIV_8, false, LRCK_DIV_32, false);
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ok &= SetI2sMode(MODE_SLAVE);
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ok &= SetI2sWordSize(WORD_SIZE_16_BITS);
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ok &= SetI2sFormat(DATA_FORMAT_I2S);
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// AIF config
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ok &= WriteReg(I2S1_SDOUT_CTRL, 0xc000);
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ok &= WriteReg(I2S1_SDIN_CTRL, 0xc000);
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ok &= WriteReg(I2S1_MXR_SRC, 0x2200);
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ok &= WriteReg(ADC_SRCBST_CTRL, 0xccc4);
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ok &= WriteReg(ADC_SRC, 0x1040);
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ok &= WriteReg(ADC_DIG_CTRL, 0x8000);
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ok &= WriteReg(ADC_APC_CTRL, 0xbbc3);
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// Path Configuration
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ok &= WriteReg(DAC_MXR_SRC, 0xcc00);
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ok &= WriteReg(DAC_DIG_CTRL, 0x8000);
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ok &= WriteReg(OMIXER_SR, 0x0081);
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ok &= WriteReg(OMIXER_DACA_CTRL, 0xf080);
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ok &= SetMode( MODE_DAC );
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return ok;
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}
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//----------------------------------------------------------------------------------------------------------------------
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void AC101::DumpRegisters() {
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for (size_t i = 0; i < ARRAY_SIZE(regs); ++i){
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Serial.print(regs[i], HEX);
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Serial.print(" = ");
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Serial.println(ReadReg(regs[i]), HEX);
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}
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}
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//----------------------------------------------------------------------------------------------------------------------
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uint8_t AC101::GetVolumeSpeaker() {
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// Times 2, to scale to same range as headphone volume
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return (ReadReg(SPKOUT_CTRL) & 31) * 2;
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}
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bool AC101::SetVolumeSpeaker(uint8_t volume) {
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// Divide by 2, as it is scaled to same range as headphone volume
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volume /= 2;
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if(volume > 31) volume = 31;
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uint16_t val = ReadReg(SPKOUT_CTRL);
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val &= ~31;
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val |= volume;
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return WriteReg(SPKOUT_CTRL, val);
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}
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//----------------------------------------------------------------------------------------------------------------------
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uint8_t AC101::GetVolumeHeadphone() {
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return (ReadReg(HPOUT_CTRL) >> 4) & 63;
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}
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bool AC101::SetVolumeHeadphone(uint8_t volume) {
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if(volume > 63) volume = 63;
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uint16_t val = ReadReg(HPOUT_CTRL);
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val &= ~63U << 4;
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val |= volume << 4;
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return WriteReg(HPOUT_CTRL, val);
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::SetI2sSampleRate(I2sSampleRate_t rate) {
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return WriteReg(I2S_SR_CTRL, rate);
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::SetI2sMode(I2sMode_t mode) {
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uint16_t val = ReadReg(I2S1LCK_CTRL);
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val &= ~0x8000;
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val |= uint16_t(mode) << 15;
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return WriteReg(I2S1LCK_CTRL, val);
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::SetI2sWordSize(I2sWordSize_t size) {
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uint16_t val = ReadReg(I2S1LCK_CTRL);
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val &= ~0x0030;
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val |= uint16_t(size) << 4;
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return WriteReg(I2S1LCK_CTRL, val);
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::SetI2sFormat(I2sFormat_t format) {
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uint16_t val = ReadReg(I2S1LCK_CTRL);
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val &= ~0x000C;
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val |= uint16_t(format) << 2;
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return WriteReg(I2S1LCK_CTRL, val);
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::SetI2sClock(I2sBitClockDiv_t bitClockDiv, bool bitClockInv, I2sLrClockDiv_t lrClockDiv, bool lrClockInv) {
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uint16_t val = ReadReg(I2S1LCK_CTRL);
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val &= ~0x7FC0;
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val |= uint16_t(bitClockInv ? 1 : 0) << 14;
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val |= uint16_t(bitClockDiv) << 9;
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val |= uint16_t(lrClockInv ? 1 : 0) << 13;
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val |= uint16_t(lrClockDiv) << 6;
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return WriteReg(I2S1LCK_CTRL, val);
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}
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//----------------------------------------------------------------------------------------------------------------------
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bool AC101::SetMode(Mode_t mode) {
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bool ok = true;
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if(MODE_LINE == mode) {
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ok &= WriteReg(ADC_SRC, 0x0408);
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ok &= WriteReg(ADC_DIG_CTRL, 0x8000);
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ok &= WriteReg(ADC_APC_CTRL, 0x3bc0);
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}
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if((MODE_ADC == mode) or (MODE_ADC_DAC == mode) or (MODE_LINE == mode)) {
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ok &= WriteReg(MOD_CLK_ENA, 0x800c);
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ok &= WriteReg(MOD_RST_CTRL, 0x800c);
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}
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if((MODE_DAC == mode) or (MODE_ADC_DAC == mode) or (MODE_LINE == mode)) {
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// Enable Headphone output
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ok &= WriteReg(OMIXER_DACA_CTRL, 0xff80);
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ok &= WriteReg(HPOUT_CTRL, 0xc3c1);
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ok &= WriteReg(HPOUT_CTRL, 0xcb00);
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delay(100);
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ok &= WriteReg(HPOUT_CTRL, 0xfbc0);
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ok &= SetVolumeHeadphone(30);
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// Enable Speaker output
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ok &= WriteReg(SPKOUT_CTRL, 0xeabd);
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delay(10);
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ok &= SetVolumeSpeaker(30);
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}
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return ok;
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}
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